About

Intelligent edge systems constitute a key growth segment within the cloud-backed cognitive IoT marketplace. The EPOCHS ("Efficient Programmability of Cognitive Heterogeneous Systems") research project at IBM (with collaborative university partners) is driven by the specific edge application domain of connected autonomous vehicles. An adjacent domain application considered was extended reality (XR), modeled by the ILLIXR project at UIUC. Our team has developed leading edge methodologies for agile software-hardware co-design of heterogeneous SoCs to support the target application domains. As part of this project, we have successfully taped out two functional EPOCHS chips in 12 nm technology and have demonstrated full-stack solutions using FPGA and ASIC versions of the chipset. Specific use cases that have been illustrated in the context of our active technology transition phase are: (a) collaborative perception, involving a pair of communicating autonomous vehicles; (b) detecting hazards while scanning for objects and vehicles during autonomous navigation; (c) sentiment analysis of human-expressed conversations or commands (using an NLP algorithm).

In this tutorial, we summarize the key innovations and open-source tools-driven agile methodology derived from this 5-year DARPA- sponsored project (2018-2023) that is now transitioning into commercially deployable solutions in partnership with clients. In particular, we will cover the following aspects of the overall topic area in considerable detail: (a) the fundamentals of Columbia's ESP-driven agile SoC methodology, with demonstrated proof points in support of 10-100X improvement in designer productivity; (b) domain-specific hardware accelerators for AI/NLP – architecture and design methodology that address customer requirements in real- time performance, energy efficiency and security; (c) intelligent task scheduling and compiler support for domain-specific SoCs targeted for the important application space of connected autonomous vehicles, easily portable across adjacent application domains.

Key Topic Areas

  • Artificial Intelligence (AI) and Natural Language Processing (NLP) hardware, with a focus on EdgeBERT software-hardware co-designed IP from Harvard.
  • Application development for connected autonomous vehicles (ERA) and extended reality (ILLIXR) – from IBM and UIUC respectively.
  • Energy efficient design with novel distributed hardware power management (DHPM) from IBM and Columbia (publication pending).
  • Agile, software-hardware co-design methodology driven by ESP from Columbia.
  • Efficient programmability via HPVM compiler technology from UIUC.
  • Intelligent task scheduling and associated software library from IBM.
  • Ontology toolset (e.g. Trireme and Novia) for efficient accelerator discovery from application source code – from Harvard, UIUC and IBM.

Tutorial Date
June 29th, 2024

Room Location
Jacarandá

Tentative Program:

Saturday, June 29thth, 2024
(all times are (GMT-3))
Location: Jacarandá
9:00 - 9:15 AM Welcoming Remarks and Overall Summary of the EPOCHS project in the context of DARPA DSSoC
Pradip Bose (IBM Research)
9:15 - 10:20 AM Application Domains of Interest (and associated characterization, modeling):
Aerial Computing - Vijay Reddi (Harvard University)
Connected Autonomous Vehicles - Aporva Amarnath (IBM Research)
Extended Reality (XR) - Qinjun Jiang, Ying Jing, Vignesh Suresh and Sarita Adve (University of Illinois at Urbana-Champaign)
10:20 - 11:10 AM HPVM: Efficient Compilation for Heterogeneous Systems
Sasa Misailovic, Sarita Adve and Vikram Adve (University of Illinois at Urbana-Champaign)
11:10 - 12:00 PM Ontology - systematic derivation of domain-specific accelerators, with simulation-based evaluation
Alper Buyuktosunoglu, David Trilla and Subhankar Pal (IBM Research)
With contributions from David Brooks and Gu-Yeon Wei (Harvard University)
12:00 - 12:30 PM ESP-driven agile SoC design methodology - with chip examples
Joseph Zuckerman and Luca Carloni (Columbia University)
12:30 - 2:00 PM Lunch
2:00 - 3:00 PM Scalable power management for AI-centric SoCs and EPOCHS Chip Demo
Karthik Swaminathan and Martin Cochet (IBM Research)
3:00 - 3:20 PM Break
3:20 - 4:05 PM Deep dive on specific AI/ML hardware accelerator designs
Thierry Tambe (Stanford University), Alexander Rush (Cornell University), David Brooks (Harvard University) and Gu-Yeon Wei (Harvard University)
4:05 - 4:50 PM Smart Scheduling for heterogeneous SoCs
Aporva Amarnath (IBM Research)
4:50 - 5:30 PM Security Issues in AI-Centric SoCs - Modeling and Mitigation
Naorin Hossain (IBM Research)
5:30 - 6:15 PM Technology transition - applying EPOCHS methodology to real “secure AI” product roadmap
Pradip Bose and Augusto Vega (IBM Research)

Organizers

Sarita Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests are at the hardware-software interface and her work has spanned computer architecture, programming languages, operating systems, and applications. Adve received the Ph.D. in Computer Science from Wisconsin in 1993 and a B.Tech. in Electrical Engineering from IIT-Bombay in 1987.

Vikram Adve is the Donald B. Gillies Professor of Computer Science at the University of Illinois at Urbana-Champaign and a Professor in Electrical and Computer Engineering. He is a Co-founder and Co-Director of the Center for Digital Agriculture and leads AIFARMS, a $20M National Artificial Intelligence Research Institute funded by NIFA and NSF. Adve’s research interests lie in developing and using compiler techniques to improve the performance, programmability and reliability of computer systems.

Pradip Bose is a Distinguished Research Staff Member and manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over thirty-three years of experience at IBM, and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds a Ph.D. degree from University of Illinois at Urbana-Champaign.

David Brooks is the Haley Family Professor of Computer Science at Harvard University. He received his B.S. in Electrical Engineering at the University of Southern California and M.A. and Ph.D. degrees in Electrical Engineering at Princeton University. His research interests include computer design at the hardware-software interface..

Luca Carloni is Professor and Chair of Computer Science at Columbia University in the City of New York, where he leads the System-Level Design Group. He received his Ph.D. in Electrical Engineering and Computer Sciences from the University of California at Berkeley. His research interests include methodologies and tools for system-on-chip platforms with emphasis on heterogeneous computing, intellectual property reuse, design of networks-on-chip, embedded software and distributed embedded systems.

Sasa Misailovic is an Associate Professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. He received his PhD from MIT in Summer 2015. His research interests include programming languages, compilers, and software engineering, with an emphasis on improving performance, energy efficiency, and resilience in the face of software errors and approximation opportunities.

Vijay Janapa Reddi is an Associate Professor at Harvard University, Vice President, and Founding Member of MLCommons. He specializes in developing mobile and edge computing platforms, as well as the Internet of Things. His work is largely based on runtime systems, computer architecture, and applied machine learning methods. He holds degrees from Harvard University, University of Colorado at Boulder, and Santa Clara University.

Ken Shepard is Lau Family Professor of Electrical Engineering and Biomedical Engineering at Columbia Univeristy, co-Director of Columbia's NeuroTechnology Center and a member of the Kavli Institute for Neuroscience at Columbia. Shepard has more than 25 years of experience in the design of analog, digital, and mixed signal integrated circuits and has pioneered many applications of semiconductors to biology including applications in single-molecule molecular diagnostics, microbiology, and neuroscience.

Gu-Yeon Wei is the Robert and Suzanne Case Professor of Electrical Engineering and Computer Science at Harvard University and currently serves as Area Chair for Electrical Engineering. He received his BS, MS, and PhD degrees in Electrical Engineering from Stanford University. His research interests span multiple layers of a computing system: mixed-signal integrated circuits, computer architecture, and design tools for efficient hardware.

Registration

The tutorial will be held in conjunction with the 51st International Symposium on Computer Architecture (ISCA 2024). Refer to the main venue to continue with the registration process.

Event Location

Hilton Buenos Aires
Macacha Güemes 351
Buenos Aires, Argentina

Check main venue site for more information.